I2C_RX_CTRL0

Macros
#define	MXC_F_I2C_RX_CTRL0_DNR_POS   0
#define	MXC_F_I2C_RX_CTRL0_DNR   ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS))
#define	MXC_F_I2C_RX_CTRL0_RXFSH_POS   7
#define	MXC_F_I2C_RX_CTRL0_RXFSH   ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RXFSH_POS))
#define	MXC_F_I2C_RX_CTRL0_RXTH_POS   8
#define	MXC_F_I2C_RX_CTRL0_RXTH   ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RXTH_POS))

Detailed Description

Receive Control Register 0.

Macro Definition Documentation

MXC_F_I2C_RX_CTRL0_DNR

#define MXC_F_I2C_RX_CTRL0_DNR   ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS))

RX_CTRL0_DNR Mask

MXC_F_I2C_RX_CTRL0_DNR_POS

#define MXC_F_I2C_RX_CTRL0_DNR_POS   0

RX_CTRL0_DNR Position

MXC_F_I2C_RX_CTRL0_RXFSH

#define MXC_F_I2C_RX_CTRL0_RXFSH   ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RXFSH_POS))

RX_CTRL0_RXFSH Mask

MXC_F_I2C_RX_CTRL0_RXFSH_POS

#define MXC_F_I2C_RX_CTRL0_RXFSH_POS   7

RX_CTRL0_RXFSH Position

MXC_F_I2C_RX_CTRL0_RXTH

#define MXC_F_I2C_RX_CTRL0_RXTH   ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RXTH_POS))

RX_CTRL0_RXTH Mask

MXC_F_I2C_RX_CTRL0_RXTH_POS

#define MXC_F_I2C_RX_CTRL0_RXTH_POS   8

RX_CTRL0_RXTH Position