PWRSEQ_LPCN

Macros
#define	MXC_F_PWRSEQ_LPCN_RAMRET_POS   0
#define	MXC_F_PWRSEQ_LPCN_RAMRET   ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_RAMRET_POS))
#define	MXC_V_PWRSEQ_LPCN_RAMRET_DIS   ((uint32_t)0x0UL)
#define	MXC_S_PWRSEQ_LPCN_RAMRET_DIS   (MXC_V_PWRSEQ_LPCN_RAMRET_DIS << MXC_F_PWRSEQ_LPCN_RAMRET_POS)
#define	MXC_V_PWRSEQ_LPCN_RAMRET_EN1   ((uint32_t)0x1UL)
#define	MXC_S_PWRSEQ_LPCN_RAMRET_EN1   (MXC_V_PWRSEQ_LPCN_RAMRET_EN1 << MXC_F_PWRSEQ_LPCN_RAMRET_POS)
#define	MXC_V_PWRSEQ_LPCN_RAMRET_EN2   ((uint32_t)0x2UL)
#define	MXC_S_PWRSEQ_LPCN_RAMRET_EN2   (MXC_V_PWRSEQ_LPCN_RAMRET_EN2 << MXC_F_PWRSEQ_LPCN_RAMRET_POS)
#define	MXC_V_PWRSEQ_LPCN_RAMRET_EN3   ((uint32_t)0x3UL)
#define	MXC_S_PWRSEQ_LPCN_RAMRET_EN3   (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 << MXC_F_PWRSEQ_LPCN_RAMRET_POS)
#define	MXC_F_PWRSEQ_LPCN_BLKDET_POS   6
#define	MXC_F_PWRSEQ_LPCN_BLKDET   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BLKDET_POS))
#define	MXC_F_PWRSEQ_LPCN_BCKGRND_POS   9
#define	MXC_F_PWRSEQ_LPCN_BCKGRND   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BCKGRND_POS))
#define	MXC_F_PWRSEQ_LPCN_FWKM_POS   10
#define	MXC_F_PWRSEQ_LPCN_FWKM   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FWKM_POS))
#define	MXC_F_PWRSEQ_LPCN_BGOFF_POS   11
#define	MXC_F_PWRSEQ_LPCN_BGOFF   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS))
#define	MXC_F_PWRSEQ_LPCN_VCOREMD_POS   20
#define	MXC_F_PWRSEQ_LPCN_VCOREMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMD_POS))
#define	MXC_F_PWRSEQ_LPCN_VREGIMD_POS   21
#define	MXC_F_PWRSEQ_LPCN_VREGIMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VREGIMD_POS))
#define	MXC_F_PWRSEQ_LPCN_VDDAMD_POS   22
#define	MXC_F_PWRSEQ_LPCN_VDDAMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS))
#define	MXC_F_PWRSEQ_LPCN_VDDIOMD_POS   23
#define	MXC_F_PWRSEQ_LPCN_VDDIOMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMD_POS))
#define	MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS   24
#define	MXC_F_PWRSEQ_LPCN_VDDIOHMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS))
#define	MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS   25
#define	MXC_F_PWRSEQ_LPCN_PORVDDIOMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS))
#define	MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS   26
#define	MXC_F_PWRSEQ_LPCN_PORVDDIOHMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS))
#define	MXC_F_PWRSEQ_LPCN_VDDBMD_POS   27
#define	MXC_F_PWRSEQ_LPCN_VDDBMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS))
#define	MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS   28
#define	MXC_F_PWRSEQ_LPCN_VRXOUTMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS))
#define	MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS   29
#define	MXC_F_PWRSEQ_LPCN_VTXOUTMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS))
#define	MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS   30
#define	MXC_F_PWRSEQ_LPCN_PDOWNDSLEN   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS))

Detailed Description

Low Power Control Register.

Macro Definition Documentation

MXC_F_PWRSEQ_LPCN_BCKGRND

#define MXC_F_PWRSEQ_LPCN_BCKGRND   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BCKGRND_POS))

LPCN_BCKGRND Mask

MXC_F_PWRSEQ_LPCN_BCKGRND_POS

#define MXC_F_PWRSEQ_LPCN_BCKGRND_POS   9

LPCN_BCKGRND Position

MXC_F_PWRSEQ_LPCN_BGOFF

#define MXC_F_PWRSEQ_LPCN_BGOFF   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS))

LPCN_BGOFF Mask

MXC_F_PWRSEQ_LPCN_BGOFF_POS

#define MXC_F_PWRSEQ_LPCN_BGOFF_POS   11

LPCN_BGOFF Position

MXC_F_PWRSEQ_LPCN_BLKDET

#define MXC_F_PWRSEQ_LPCN_BLKDET   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BLKDET_POS))

LPCN_BLKDET Mask

MXC_F_PWRSEQ_LPCN_BLKDET_POS

#define MXC_F_PWRSEQ_LPCN_BLKDET_POS   6

LPCN_BLKDET Position

MXC_F_PWRSEQ_LPCN_FWKM

#define MXC_F_PWRSEQ_LPCN_FWKM   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FWKM_POS))

LPCN_FWKM Mask

MXC_F_PWRSEQ_LPCN_FWKM_POS

#define MXC_F_PWRSEQ_LPCN_FWKM_POS   10

LPCN_FWKM Position

MXC_F_PWRSEQ_LPCN_PDOWNDSLEN

#define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS))

LPCN_PDOWNDSLEN Mask

MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS

#define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS   30

LPCN_PDOWNDSLEN Position

MXC_F_PWRSEQ_LPCN_PORVDDIOHMD

#define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS))

LPCN_PORVDDIOHMD Mask

MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS

#define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS   26

LPCN_PORVDDIOHMD Position

MXC_F_PWRSEQ_LPCN_PORVDDIOMD

#define MXC_F_PWRSEQ_LPCN_PORVDDIOMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS))

LPCN_PORVDDIOMD Mask

MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS

#define MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS   25

LPCN_PORVDDIOMD Position

MXC_F_PWRSEQ_LPCN_RAMRET

#define MXC_F_PWRSEQ_LPCN_RAMRET   ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_RAMRET_POS))

LPCN_RAMRET Mask

MXC_F_PWRSEQ_LPCN_RAMRET_POS

#define MXC_F_PWRSEQ_LPCN_RAMRET_POS   0

LPCN_RAMRET Position

MXC_F_PWRSEQ_LPCN_VCOREMD

#define MXC_F_PWRSEQ_LPCN_VCOREMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMD_POS))

LPCN_VCOREMD Mask

MXC_F_PWRSEQ_LPCN_VCOREMD_POS

#define MXC_F_PWRSEQ_LPCN_VCOREMD_POS   20

LPCN_VCOREMD Position

MXC_F_PWRSEQ_LPCN_VDDAMD

#define MXC_F_PWRSEQ_LPCN_VDDAMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS))

LPCN_VDDAMD Mask

MXC_F_PWRSEQ_LPCN_VDDAMD_POS

#define MXC_F_PWRSEQ_LPCN_VDDAMD_POS   22

LPCN_VDDAMD Position

MXC_F_PWRSEQ_LPCN_VDDBMD

#define MXC_F_PWRSEQ_LPCN_VDDBMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS))

LPCN_VDDBMD Mask

MXC_F_PWRSEQ_LPCN_VDDBMD_POS

#define MXC_F_PWRSEQ_LPCN_VDDBMD_POS   27

LPCN_VDDBMD Position

MXC_F_PWRSEQ_LPCN_VDDIOHMD

#define MXC_F_PWRSEQ_LPCN_VDDIOHMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS))

LPCN_VDDIOHMD Mask

MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS

#define MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS   24

LPCN_VDDIOHMD Position

MXC_F_PWRSEQ_LPCN_VDDIOMD

#define MXC_F_PWRSEQ_LPCN_VDDIOMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMD_POS))

LPCN_VDDIOMD Mask

MXC_F_PWRSEQ_LPCN_VDDIOMD_POS

#define MXC_F_PWRSEQ_LPCN_VDDIOMD_POS   23

LPCN_VDDIOMD Position

MXC_F_PWRSEQ_LPCN_VREGIMD

#define MXC_F_PWRSEQ_LPCN_VREGIMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VREGIMD_POS))

LPCN_VREGIMD Mask

MXC_F_PWRSEQ_LPCN_VREGIMD_POS

#define MXC_F_PWRSEQ_LPCN_VREGIMD_POS   21

LPCN_VREGIMD Position

MXC_F_PWRSEQ_LPCN_VRXOUTMD

#define MXC_F_PWRSEQ_LPCN_VRXOUTMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS))

LPCN_VRXOUTMD Mask

MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS

#define MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS   28

LPCN_VRXOUTMD Position

MXC_F_PWRSEQ_LPCN_VTXOUTMD

#define MXC_F_PWRSEQ_LPCN_VTXOUTMD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS))

LPCN_VTXOUTMD Mask

MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS

#define MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS   29

LPCN_VTXOUTMD Position

MXC_S_PWRSEQ_LPCN_RAMRET_DIS

#define MXC_S_PWRSEQ_LPCN_RAMRET_DIS   (MXC_V_PWRSEQ_LPCN_RAMRET_DIS << MXC_F_PWRSEQ_LPCN_RAMRET_POS)

LPCN_RAMRET_DIS Setting

MXC_S_PWRSEQ_LPCN_RAMRET_EN1

#define MXC_S_PWRSEQ_LPCN_RAMRET_EN1   (MXC_V_PWRSEQ_LPCN_RAMRET_EN1 << MXC_F_PWRSEQ_LPCN_RAMRET_POS)

LPCN_RAMRET_EN1 Setting

MXC_S_PWRSEQ_LPCN_RAMRET_EN2

#define MXC_S_PWRSEQ_LPCN_RAMRET_EN2   (MXC_V_PWRSEQ_LPCN_RAMRET_EN2 << MXC_F_PWRSEQ_LPCN_RAMRET_POS)

LPCN_RAMRET_EN2 Setting

MXC_S_PWRSEQ_LPCN_RAMRET_EN3

#define MXC_S_PWRSEQ_LPCN_RAMRET_EN3   (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 << MXC_F_PWRSEQ_LPCN_RAMRET_POS)

LPCN_RAMRET_EN3 Setting

MXC_V_PWRSEQ_LPCN_RAMRET_DIS

#define MXC_V_PWRSEQ_LPCN_RAMRET_DIS   ((uint32_t)0x0UL)

LPCN_RAMRET_DIS Value

MXC_V_PWRSEQ_LPCN_RAMRET_EN1

#define MXC_V_PWRSEQ_LPCN_RAMRET_EN1   ((uint32_t)0x1UL)

LPCN_RAMRET_EN1 Value

MXC_V_PWRSEQ_LPCN_RAMRET_EN2

#define MXC_V_PWRSEQ_LPCN_RAMRET_EN2   ((uint32_t)0x2UL)

LPCN_RAMRET_EN2 Value

MXC_V_PWRSEQ_LPCN_RAMRET_EN3

#define MXC_V_PWRSEQ_LPCN_RAMRET_EN3   ((uint32_t)0x3UL)

LPCN_RAMRET_EN3 Value