SPI_CLK_CFG

Macros
#define	MXC_F_SPI_CLK_CFG_LO_POS   0
#define	MXC_F_SPI_CLK_CFG_LO   ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS))
#define	MXC_V_SPI_CLK_CFG_LO_DIS   ((uint32_t)0x0UL)
#define	MXC_S_SPI_CLK_CFG_LO_DIS   (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS)
#define	MXC_F_SPI_CLK_CFG_HI_POS   8
#define	MXC_F_SPI_CLK_CFG_HI   ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS))
#define	MXC_V_SPI_CLK_CFG_HI_DIS   ((uint32_t)0x0UL)
#define	MXC_S_SPI_CLK_CFG_HI_DIS   (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS)
#define	MXC_F_SPI_CLK_CFG_SCALE_POS   16
#define	MXC_F_SPI_CLK_CFG_SCALE   ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS))

Detailed Description

Register for controlling SPI clock rate.

Macro Definition Documentation

MXC_F_SPI_CLK_CFG_HI

#define MXC_F_SPI_CLK_CFG_HI   ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS))

CLK_CFG_HI Mask

MXC_F_SPI_CLK_CFG_HI_POS

#define MXC_F_SPI_CLK_CFG_HI_POS   8

CLK_CFG_HI Position

MXC_F_SPI_CLK_CFG_LO

#define MXC_F_SPI_CLK_CFG_LO   ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS))

CLK_CFG_LO Mask

MXC_F_SPI_CLK_CFG_LO_POS

#define MXC_F_SPI_CLK_CFG_LO_POS   0

CLK_CFG_LO Position

MXC_F_SPI_CLK_CFG_SCALE

#define MXC_F_SPI_CLK_CFG_SCALE   ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS))

CLK_CFG_SCALE Mask

MXC_F_SPI_CLK_CFG_SCALE_POS

#define MXC_F_SPI_CLK_CFG_SCALE_POS   16

CLK_CFG_SCALE Position

MXC_S_SPI_CLK_CFG_HI_DIS

#define MXC_S_SPI_CLK_CFG_HI_DIS   (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS)

CLK_CFG_HI_DIS Setting

MXC_S_SPI_CLK_CFG_LO_DIS

#define MXC_S_SPI_CLK_CFG_LO_DIS   (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS)

CLK_CFG_LO_DIS Setting

MXC_V_SPI_CLK_CFG_HI_DIS

#define MXC_V_SPI_CLK_CFG_HI_DIS   ((uint32_t)0x0UL)

CLK_CFG_HI_DIS Value

MXC_V_SPI_CLK_CFG_LO_DIS

#define MXC_V_SPI_CLK_CFG_LO_DIS   ((uint32_t)0x0UL)

CLK_CFG_LO_DIS Value