AES_STATUS

Macros
#define	MXC_F_AES_STATUS_BUSY_POS   0
#define	MXC_F_AES_STATUS_BUSY   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS))
#define	MXC_F_AES_STATUS_INPUT_EM_POS   1
#define	MXC_F_AES_STATUS_INPUT_EM   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS))
#define	MXC_F_AES_STATUS_INPUT_FULL_POS   2
#define	MXC_F_AES_STATUS_INPUT_FULL   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS))
#define	MXC_F_AES_STATUS_OUTPUT_EM_POS   3
#define	MXC_F_AES_STATUS_OUTPUT_EM   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS))
#define	MXC_F_AES_STATUS_OUTPUT_FULL_POS   4
#define	MXC_F_AES_STATUS_OUTPUT_FULL   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS))

Detailed Description

AES Status Register.

Macro Definition Documentation

MXC_F_AES_STATUS_BUSY

#define MXC_F_AES_STATUS_BUSY   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS))

STATUS_BUSY Mask

MXC_F_AES_STATUS_BUSY_POS

#define MXC_F_AES_STATUS_BUSY_POS   0

STATUS_BUSY Position

MXC_F_AES_STATUS_INPUT_EM

#define MXC_F_AES_STATUS_INPUT_EM   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS))

STATUS_INPUT_EM Mask

MXC_F_AES_STATUS_INPUT_EM_POS

#define MXC_F_AES_STATUS_INPUT_EM_POS   1

STATUS_INPUT_EM Position

MXC_F_AES_STATUS_INPUT_FULL

#define MXC_F_AES_STATUS_INPUT_FULL   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS))

STATUS_INPUT_FULL Mask

MXC_F_AES_STATUS_INPUT_FULL_POS

#define MXC_F_AES_STATUS_INPUT_FULL_POS   2

STATUS_INPUT_FULL Position

MXC_F_AES_STATUS_OUTPUT_EM

#define MXC_F_AES_STATUS_OUTPUT_EM   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS))

STATUS_OUTPUT_EM Mask

MXC_F_AES_STATUS_OUTPUT_EM_POS

#define MXC_F_AES_STATUS_OUTPUT_EM_POS   3

STATUS_OUTPUT_EM Position

MXC_F_AES_STATUS_OUTPUT_FULL

#define MXC_F_AES_STATUS_OUTPUT_FULL   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS))

STATUS_OUTPUT_FULL Mask

MXC_F_AES_STATUS_OUTPUT_FULL_POS

#define MXC_F_AES_STATUS_OUTPUT_FULL_POS   4

STATUS_OUTPUT_FULL Position